The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices, such as memory devices, having contact plugs passing through insulating layers and methods of fabricating the same.
In semiconductor memory devices, a static random access memory (SRAM) device may offer advantages of lower power consumption and faster operating speed as compared to a dynamic random access memory (DRAM) device. Accordingly, the SRAM may be widely used for cache memory in computers and/or portable devices.
A unit cell of the SRAM device may be categorized as a load resistor SRAM cell or a complementary metal-oxide-semiconductor (CMOS) SRAM cell. The load resistor SRAM cell typically employs a high load resistor as a load device, while the CMOS SRAM cell typically employs a p-channel metal-oxide-semiconductor (PMOS) transistor as a load device.
CMOS SRAM cells may be categorized into two types. One type of CMOS SRAM cell is a thin film transistor (TFT) SRAM cell, which may employ TFTs stacked on a semiconductor substrate as the load device. Another is a bulk CMOS SRAM cell, which may employ bulk transistors formed at a semiconductor substrate as the load device.
A bulk CMOS SRAM cell may exhibit higher cell stability as compared to TFT SRAM cell and the load resistor SRAM cell. In other words, the bulk CMOS SRAM cell may have excellent low voltage characteristics and low stand-by current. This may be because the transistors that make up the bulk CMOS SRAM cell are typically formed of a single crystal silicon substrate. In contrast, the TFTs of the TFT SRAM cells are typically formed using a polysilicon layer as a body layer. However, a bulk CMOS SRAM cell may have lower integration density as well as weaker latch-up immunity as compared to a TFT SRAM cell. Therefore, in order to produce a highly integrated SRAM device having high reliability, the characteristics of the load transistors employed in the TFT SRAM cells may need to be improved.
Semiconductor devices having TFTs stacked on a semiconductor substrate are described in U.S. Pat. No. 6,022,766 to Chen et al. According to Chen et al., an improved field effect transistor (FET) structure comprises: a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFTs can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Chen et al. also discloses a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell.
A body layer of a TFT may be formed by depositing an amorphous silicon layer on the semiconductor substrate having the metal plug, and by crystallizing the amorphous silicon layer using a thermal treatment process. The body layer may be a polysilicon layer having large grains. As such, it may be difficult to convert the body layer into a perfect single crystal silicon layer. Consequently, it may be difficult to form TFTs having electrical characteristics comparable to that of a bulk transistor. Accordingly, there is a need for techniques for enhancing characteristics of a TFT stacked over a semiconductor substrate.
Techniques for forming contact plugs using a self-aligned contact technique are disclosed in Korean patent publication No. 2001-66390 to Chung et al., entitled “Methods of fabricating a contact plug of a semiconductor device using a selective epitaxial growth technique”. FIGS. 1 and 2 are cross-sectional views illustrating operations for fabricating a contact plug described in the Korean patent publication No. 2001-66390.
Referring to FIG. 1, a field oxide layer, i.e., an isolation layer 12, is formed at a predetermined region of a semiconductor substrate 10, such as a silicon substrate, to define an active region. Gate patterns are formed, crossing over the active region and the isolation layer 12. Each of the gate patterns includes a gate electrode 14 and a hard mask pattern 16 that are sequentially stacked. The hard mask pattern 16 is formed from a silicon nitride layer. Spacers 18 are formed on sidewalls of the gate patterns. The spacers 18 are also formed of a silicon nitride layer. An inter-layer insulating layer 20 is formed on the substrate having the spacers 18, and the inter-layer insulating layer 20 is planarized using a chemical mechanical polishing (CMP) technique until the hard mask patterns 16 are exposed. The planarized inter-layer insulating layer 20 is patterned to form self-aligned contact holes that expose the active region between the gate patterns.
Referring to FIG. 2, an undoped silicate glass (USG) layer is formed on an entire surface of the substrate having the self-aligned contact holes. The USG layer may be formed using a plasma-enhanced chemical vapor deposition (PECVD) technique. When the self-aligned contact holes have an aspect ratio of 4 or more, the USG layer on the bottom surfaces of the self-aligned contact holes is formed to be thinner than the USG layer on the planarized inter-layer insulating layer 20 and the hard mask patterns 16. Accordingly, even though the USG layer is anisotropically etched until the active region between the gate patterns is exposed, the spacers 18 and the hard mask patterns 16 are still covered with the anisotropically etched USG layer 22′ as shown in FIG. 2. Contact plugs 24, i.e., silicon plugs, are formed in the self-aligned contact holes surrounded by the anisotropically etched USG layer 22′ using a selective epitaxial growth (SEG) technique.
The anisotropically etched USG layer 22′ is formed in order to enhance a selectivity with respect to silicon during the SEG process. If the SEG process is performed on the substrate where the hard mask patterns 16, the spacers 18 and the planarized inter-layer insulating layer 20 are exposed, it may be difficult to find out an optimal process condition that does not cause crystalline defects, such as dislocations and/or stacking faults, in the silicon plugs 24. Accordingly, when the USG layer 22′ is formed, it can be easier to obtain an optimal process condition of the SEG process suitable for formation of the silicon plugs 24 with reduced crystalline defects.
According to Chung et at as described above, because of the presence of the anisotropically etched USG layer, silicon plugs with reduced crystalline defects may be formed in self-aligned contact holes. However, when the USG layer is formed using a source material such as tetra-ethyl-ortho-silicate (TEOS), the USG layer may contain carbon atoms. In this case, it can difficult to form a high performance TFT on the USG layer. This is because carbon atoms can penetrate into the body layer of the TFT to degrade a leakage current characteristic of the source and drain regions of the TFT. Alternatively, when a dense inorganic oxide layer, such as a high-density plasma (HDP) oxide layer, is formed instead of the USG layer, a strong physical stress may be applied to the silicon plugs, which can generate crystalline defects in the silicon plugs.